`timescale 1ns / 1ps

`include "defines.v"
module uart_tx_tb ();
reg clk_50m = 0;
reg rst_n = 0;
reg [7:0] data = 0;
reg enable = 0;
wire busy, tx;

initial begin
    $dumpfile("output/uart_tx_tb.vcd");
    $dumpvars(0, uart_tx_tb);
end

initial begin
    #100 rst_n = 1;
    #10  data = 8'b1010_0101; enable = 1;
    #20	 data = 8'b0000_0000; enable = 0;

    #(20*2604*11) data = 8'b0011_0010; enable = 1;
    #20	 data = 8'b0000_0000; enable = 0;
    #(20*2604*11) $stop;
end

always #10 clk_50m = ~clk_50m;

uart_tx	#(
  .CLK_FREQ	(50_000_000),
  .BSP		(19200),
  .PARITY	(`EVEN),
  .DATA_BITS(8),
  .STOP_BITS(1)
)
inst_uart_tx(
    .clk_50m			(clk_50m),
    .rst_n				(rst_n),
    .data				(data),
    .enable				(enable),
    .busy				(busy),
    .tx					(tx)
);

endmodule  //uart_tx_tb